Adlink VPX6000 Uživatelský manuál stáhnout pdf (Strana 40)

28 Board Interfaces

Table 4-3: P3 Connector Signal Descriptions

Signal I/O Description

NA_REAR-RX[P/N]1 I Node A PCIe port1 receive LAN from backplane to PCH

NA_REAR-TX[P/N]1 O Node A PCIe port1 transmit LAN from PCH to backplane

NA_REAR-RX[P/N]2 I Node A PCIe port2 receive LAN from backplane to PCH

NA_REAR-TX[P/N]2 O Node A PCIe port2 transmit LAN from PCH to backplane

NA_REAR_GPIO[0:7] I/O Node A General Purpose IO, Channels 0-7

NA_USB3_RX_2[P/N] I Node A USB 3.0 port receive lane from backplane to PCH

NA_USB3_TX_2[P/N] O Node A USB 3.0 port transmit lane from PCH to backplane

NA_USB3_RX_5[P/N] I Node A USB 3.0 port receive lane from backplane to PCH

NA_USB3_TX_5[P/N] O Node A USB 3.0 port transmit lane from PCH to backplane

NA_RTM_BOOT# I Node A boot up from RTM BIOS when this pin pull low

NA_EXT_NODE_RST I Node A reset input

NA_SATA_RX[P/N]3 I Node A SATA 6Gb/s port receive lane from backplane to PCH

NA_SATA_TX[P/N]3 O Node A SATA 6Gb/s port transmit lane from PCH to backplane

NA_SPI_* I/O Node A SPI bus for RTM BIOS

NA_LPC_* I/O Node A LPC bus for RTM debug port

NA_MSCLK I/O Node A PS2 bus mouse signal clock

NA_MSDATA I/O Node A PS2 bus mouse signal data

NA_KBCLK I/O Node A PS2 bus keyboard signal clock

NA_KBDATA I/O Node A PS2 bus keyboard signal data

PROG_* I/O IPMC JTAG PORT

REAR_LANSW_UART_TX /

REAR_LANSW_UART_RX

I/O COM port for GLAN Switch hub software develop

P12V I +12V Power source

P5V I +5V Power source

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Adlink VPX6000 Uživatelský manuál Strana 40